Conventional technology is described in pages 5-7, PLL (Phase-Locked-Loop) Application Circuit, Sep. 10, 1979, Takeshi Yanagisama, from Sogo-Electric Publication Co. A phase-locked loop is a circuit for synchronizing a variable local oscillator with the phase of a transmitted signal. It is widely used in space communication for coherent carrier tracking, and threshold extension, but synchronization and symbol synchronization.
The conventional clock generating circuit includes a phase comparator to which a base clock (input clock) is supplied, a loop filter and a voltage-controlled oscillator. In the clock generating circuit, the phase comparator compares the phases of the base clock and an output clock to generate a signal corresponding to the phase difference between them. The loop filter removes high frequency component from the signal to generate a low frequency signal. The voltage-controlled oscillator is controlled with the low frequency signal so that the phase difference between the output clock and the base clock approximates zero.
According to the above-described conventional technology, however, it is difficult to generate an output clock having a frequency that is much different from the base clock (input clock). In other words, for generating such an output clock with the conventional circuit, it is required to adjust or control many components precisely. On the other hand, if digital circuits are used, it is easy to generate such an output clock, however, the circuitry becomes complicated in structure. Consequently, it is difficult to put the conventional circuit in practical use for generating such an output clock having a frequency that is much different from the base clock (input clock).